In electronic component fabrication processes, elements are frequently used that consist of a layer made from a first material that supports a pattern made from a second material, for example in the form of a thin layer. This type of structure is seen in particular in the silicon-on-insulator (SOI) technology, as described in patent application FR 2 827 705 for the production of a transistor, for example. In this technique, a buried insulative material layer separates the pattern, which is part of the electronically active portion (for example a transistor), from the solid silicon substrate. During the fabrication of the thin layer element, it may be necessary to increase the thickness of the pattern locally, for example by means of an epitaxial technique. At this stage, the buried layer of insulative material is supporting a thin silicon pattern. To clean this structure, it must be heated to a high temperature to bring about desorption of species.
Applying a high temperature (typically of the order of 850° C.) activates the phenomenon of surface diffusion. If the pattern is very thin (typically about 10 nm thick or even less, which is increasingly the case with the ongoing reduction in the size of microelectronic components), this diffusion can convert the pattern, which is initially in the form of a uniform block, into a set of separate crystals, which correspond to the equilibrium form that minimizes the energy of the system.
This kind of phenomenon, known as agglomeration, is disastrous for the continuation of the fabrication process. Therefore, a need exists for a fabrication process that avoids agglomeration.